This invention relates to semiconductor memory devices and, more particularly, to a precharge system of the divided bit line method in a Static Random Access Memory (hereinafter SRAM).
Development is well underway of SRAM devices having high density, high speed and low power consumption. High speed and low active current consumption can be obtained by employing an address transition detection method in the bit line precharge circuit of a SRAM. However, a high density of memory cells increases the number of bit lines to be so precharged and, thus, the active current, and creates a problem from the bit line peak current. That is, the charging current in a precharging cycle on the long and large capacitance bit lines that result from the high density takes so great a portion of the active current of the total chip that the peak current of the bit lines then causes fluctuations in Vcc and Vss that have a bad influence on the stability of operation. Consequently, the total and peak precharging current for the bit lines should be reduced for stable operation of the chip.
A method for reducing the power consumption in a conventional SRAM precharges every bit line in sequentially selected blocks (i.e., the parts of the memory cell array respectively controlled by the word lines) as described in IEEE Journal of Solid-State Circuits, Vol. 20, No. 5, Oct. 1985, pp 941. However, with this method, the reduction of the active current consumption is limited by the large number of bit lines in each block of a high density SRAM.